SHORT SUMMARY
This EU-funded co-operative research project addresses the development of a digitiser based on state-of-the-art analogue-to-digital converters (ADCs), operating from DC to 100 kHz. The digitiser should meet the demands for linearity, noise, and overall accuracy of high-level measurement applications that cannot be met using currently available devices. Its aim is to establish the foundations for the development, in a follow-on project, of a digitizer with reliable performance at the 8 digit level.
Overall, the project seeks to provide the necessary proof-of-concept on key solutions to underpin the development of a digitiser with a performance superior to those currently available.
Start date : 01 June 2023
Duration: 36 months
The research will comprise 4 main activities as shown
BEYOND THE STATE OF THE ART
PROJECT OBJECTIVES
TO IDENTIFY ...
at least 2 novel metrology grade ADC architectures for the DC to 100 kHz frequency band and develop comprehensive digital models covering integrating ADC (IADC), Sigma-Delta (ΔΣ) and at least 1 mixed design. The models will include first and second order error mechanisms. This includes identifying key performance targets such as measurement error below 1 part per million, comparing the performance of the ADC architectures, and mitigating and/or compensating for their non-ideal behaviour by means of simulations.
TO ASSESS ...
at least 2 designs for novel amplifiers (composite operational amplifiers (COPAs)) for integrator and front-end digitiser circuitry with zero drift, extremely high gain, low noise and error below 1 ppm, and to develop the metrological tools to evaluate the amplifier’s performance. Additionally, to identify metrological methods for characterisation of resistors and capacitors for the amplifier’s stability, tracking and nonlinear behaviour down to and below -120 dB total harmonic distortion (THD) and electronic switches for their injection currents and transients’ stability.
TO DESIGN ...
and develop an ultra-quiet and stable low noise power supply, supplied from the mains supply but with negligible line interference noise, and applicable for all voltage and current spans needed by the metrology grade ADC architectures identified in objective 1.
TO DEVELOP ...
a precision (< 50 ps jitter) timing solution for the ADC architectures identified in objective 1, with a galvanically isolated external trigger, lock-in and internal clock frequency output, and to develop the metrological tools such as jitter and synchronisation measurement to evaluate ADC architectures’ timing performance.
TO FACILITATE ...
the take up and long-term operation of the capabilities, technology and measurement infrastructure developed in the project by the measurement supply chain (NMIs/DIs, calibration and testing laboratories), and end users (e.g. electrical power generators, manufacturers of medical imaging devices, ADC and DMM industry). The approach will be discussed within the consortium and with other EURAMET NMIs/DIs, EURAMET TCs or EMNs, to ensure that a coordinated and optimised approach to the development of traceability in this field is developed for Europe as a whole.
PROJECT TEAM
Kick-off Meeting, Dublin – 13-14 Jun 2023
Mid-term Meeting, SIQ, Ljubljana, 2 - 3 Dec 2024
M27 online Meeting, 23 Sep 2025
M9 online Meeting, 29 Feb 2024
M36 final Meeting, 14 May 2026
(and... photos from the main meetings)
Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or EURAMET. Neither the European Union nor the granting authority can be held responsible for them.
The project (22RPT02 True8DIGIT) has received funding from the European Partnership on Metrology, co-financed from the European Union’s Horizon Europe Research and Innovation Programme and by the Participating States.The UK participant in Horizon Europe Project 22RPT02 True8DIGIT is supported by UKRI grant number 10,084,012 (Signal Conversion Ltd).
